1. Field of the Invention
The present invention relates to a memory controlling device, and particularly to a memory controlling device generating a plurality of commands simultaneously.
2. Description of the Related Art
Traditionally, a memory controller generating a command for a DRAM (Dynamic Random Access Memory) while operating at the same frequency as a memory clock of the DRAM has been used as a memory controller for controlling access to the DRAM. There has recently been a desire for a memory controller generating commands at a frequency lower than that of the memory clock due to increase in speed of the memory clock in an arithmetic processing device. As this memory controller, a memory controller has been proposed which issues 2N (N is an integer of two or more) phases of a control signal supplying a command for a DRAM while operating at 1/2N of frequency of a memory clock (see Japanese Patent Laid-Open No. 2008-225775 (FIG. 1), for example). This memory controller issues 2N phases of a control signal designating operation of the DRAM while operating at 1/2N of the frequency of the memory clock, and converts the control signal into 1 phase in a memory interface circuit.